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CY2267
Pentium(R), Pentium(R) Pro, and Cyrix(R) 6x86 Compatible Clock Synthesizer/Driver
Features
* Complete clock solution to meet requirements of Pentium(R), Pentium(R) Pro, or Cyrix(R) 6x86 motherboards including dual-processor and SDRAM designs -- Sixteen CPU clock outputs, up to 66.66 MHz (see Function Table) -- One synchronous PCI clock output -- One USB clock at 48 MHz, meets Intel's accuracy, jitter, as well as rise and fall time requirements -- One I/O clock at 24 MHz -- One Ref. clock at 14.318 MHz * Two dedicated, independent Frequency Select inputs (internal pull-up) ease system design, enable in-system frequency changes, and support OE control * Low CPU clock jitter 200 ps cycle-to-cycle * Low skew outputs -- 250 ps between CPU clocks -- 1ns-3ns skew between CPU and PCI clocks for compatibility with SiS 55XX as well as Intel 82430TX, 82430HX, and 82430VX chipsets (CY2267-1) Improved output drivers are designed for low EMI Meets Pentium and Pentium Pro power-up stabilization requirements 3.3V operation, 5V tolerant inputs Available in space-saving 34-pin SSOP package
Functional Description
The CY2267 is a low-cost Clock Synthesizer/Driver chip for a Pentium, Pentium Pro, or Cyrix 6x86-based motherboard. The CY2267 outputs sixteen CPU clocks, twelve of which can be used to support up to three SDRAM modules. The PCI clock output can be buffered with an external, low-cost Zero Delay Buffer (CY2305/9), thus providing a complete solution for 82430TX desktop systems. The CPU clocks of the CY2267 have less than 200 ps cycle-to-cycle jitter. Both the CPU and PCI clocks have a slew rate of greater than 1V/ns. The USB clock meets Intel's accuracy, jitter, and rise and fall time requirements. All CPU clocks support fast clock stabilization on power-up (< 2 ms). Additionally, two dedicated Frequency Select inputs are used for Output Enable control and setting the CPU clock output frequencies. The CY2267 clock outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY2267 to have lower EMI than clock devices from other manufacturers. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more information on recommended system layout techniques. The CY2267 accepts a 14.318 MHz reference crystal or clock as its input and runs off a 3.3V supply. The CY2267 is available in a space-saving, low-cost 34-pin SSOP package and is pin-compatible with the CY2264 and CY2265.
* * * *
Logic Block Diagram
REFCLK (14.318MHz) XTALIN XTALOUT
14.318 MHz OSC. CPU PLL /2 ROM Delay (-1only)
Pin Configuration
VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Top View SSOP
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 2267-b S2 REFCLK VDD IOCLK USBCLK VSS PCICLK CPUCLK13 VDD CPUCLK12 CPUCLK11 VSS CPUCLK10 CPUCLK9 VSS CPUCLK14 CPUCLK8
CPUCLK [1-16]
XTALIN XTALOUT VSS CPUCLK16 CPUCLK1 CPUCLK2
S1 S2
SYS PLL /2
/2
IOCLK (24MHz)
VDD CPUCLK3 CPUCLK4
USBCLK (48MHz)
VSS CPUCLK5 CPUCLK6 VDD S1
PCICLK
CPUCLK15 CPUCLK7
2267-a
Intel and Pentium are registered trademarks of Intel Corporation. Cyrix is a registered trademark of Cyrix Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 September 1996 - Revised June 12, 1997
CY2267
Pin Summary
Name VDD XTALIN[1] XTALOUT VSS CPUCLK16 CPUCLK1 CPUCLK2 VDD CPUCLK3 CPUCLK4 VSS CPUCLK5 CPUCLK6 VDD S1 CPUCLK15 CPUCLK7 CPUCLK8 CPUCLK14 VSS CPUCLK9 CPUCLK10 VSS CPUCLK11 CPUCLK12 VDD CPUCLK13 PCICLK VSS USBCLK IOCLK VDD REFCLK S2
[1]
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Description Voltage supply Reference crystal input Reference crystal feedback Ground CPU clock output CPU clock output CPU clock output Voltage supply CPU clock output CPU clock output Ground CPU clock output CPU clock output Voltage supply CPU clock select input, bit 1 (internal pull-up resistor to VDD) CPU clock output CPU clock output CPU clock output CPU clock output Ground CPU clock output CPU clock output Ground CPU clock output CPU clock output Voltage supply CPU clock output PCI clock output Ground USB clock output, 48 MHz I/O clock output, 24 MHz Voltage supply Reference clock output (14.318 MHz) for ISA slots (drives CLOAD = 45 pF) CPU clock select input, bit 2 (internal pull-up resistor to VDD)
Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 17 pF.
2
CY2267
Function Table
S2 0 0 1 1 0 1 0 1 S1 XTALIN 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz CPUCLK[1-16] Hi-Z 66.67 MHz 50.0 MHz 60.0 MHz PCICLK Hi-Z 33.33 MHz 25.0 MHz 30.0 MHz REFCLK Hi-Z 14.318 MHz 14.318 MHz 14.318 MHz USBCLK Hi-Z 48 MHz 48 MHz 48 MHz IOCLK Hi-Z 24 MHz 24 MHz 24 MHz
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK CPUCLK USBCLK IOCLK
[2]
Target Frequency (MHz) 50.0 66.67 60.0 48.0 24.0
Actual Frequency (MHz) 49.93 66.56 60.0 48.008 24.004 -1399 -1597 0 167 167
PPM
Notes: 2. Meets Intel USB clock requirements.
CPU and PCI Clock Driver Strengths
* Matched impedances on both rising and falling edges on the output drivers * Output impedance: 25 (typical) measured at 1.5V.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ................................................. -0.5 to +7.0V Input Voltage ..............................................-0.5V to VDD+0.5 Storage Temperature (Non-Condensing)... -65C to +150C Max. Soldering Temperature (10 sec)...................... +260C Junction Temperature .............................................. +150C Package Power Dissipation.............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015)
Operating Conditions[3]
Parameter VDD TA CL Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK PCICLK USBCLK IOCLK REFCLK Reference Frequency, Oscillator Nominal Value 14.318 Description Min. 3.135 0 Max. 3.6 70 30 30 20 20 45 14.318 MHz Unit V C pF
f(REF)
Note: 3. Electrical parameters are guaranteed with these operating conditions.
3
CY2267
Electrical Characteristics VDD = 3.135V to 3.6V, TA = 0C to +70C
Parameter VIH VIL VOH Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Test Conditions Except Crystal Inputs Except Crystal Inputs VDD = VDD Min. IOH = 12 mA IOH = 12 mA IOH = 8 mA IOH = 8 mA IOH = 12 mA VOL Low-level Output Voltage VDD = VDD Min. IOL = 12 mA IOL = 12 mA IOL = 8 mA IOL = 8 mA IOL = 12 mA IIH IIL IOZ IDD IDD Input High Current Input Low Current Output Leakage Current Power Supply Current Power Supply Current VIH = VDD VIL = 0V Three-state VDD = 3.6V, V IN = 0 or VDD, Loaded Outputs, CPU clocks = 66.67 MHz VDD = 3.6V, V IN = 0 or VDD, Unloaded Outputs -10 CPUCLK PCICLK USBCLK IOCLK REFCLK CPUCLK PCICLK USBCLK IOCLK REFCLK 10 100 +10 180 120 A A A mA mA 0.4 V 2.4 Min. 2.0 0.8 Max. Unit V V V
4
CY2267
Switching Characteristics[4]
Parameter t1 t1C t1C t1D t1D t2 t2 t2 t3 t3 t4 t4 t5 t6 t7 t7 Output All CPUCLK PCICLK CPUCLK PCICLK CPUCLK PCICLK REFCLK CPUCLK USBCLK, IOCLK CPUCLK USBCLK, IOCLK CPUCLK CPUCLK, PCICLK CPUCLK USBCLK, IOCLK, PCICLK CPUCLK PCICLK Description Output Duty Cycle
[5]
Test Conditions t1 = t1A / t1B Measured at 2.4V, 66.67 MHz Measured at 2.4V, 33.33 MHz Measured at 0.4V, 66.67 MHz Measured at 0.4V, 33.33 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V Measured between 2.0V and 0.8V Measured at 1.5V Measured at 1.5V CPU Clock jitter USB Clock, I/O Clock, and PCI Clock jitter CPU clock stabilization from power-up PCI clock stabilization from power-up
Min. 45 5.0 12.0 5.0 12.0 1.0 1.0 0.5 0.3
Typ. 50
Max. 55
Unit % ns ns ns ns
CPU Clock HIGH Time PCI Clock HIGH Time[6] CPU Clock LOW Time PCI Clock LOW Time
[6]
CPU Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate Reference Clock Rising and Falling Edge Rate CPU Clock Rise Time USB Clock and I/O Clock Rise Time CPU Clock Fall Time USB Clock and I/O Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew (CY2267-1) Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter
4.0 4.0
V/ns V/ns V/ns
1.2 1.2
ns ns ns ns ps ns ps ps
0.3
1.2 1.2 100 250 3.0 200 500
1.0
2.0
t8 t8
Power-up Time Power-up Time
2 2
ms ms
Notes: 4. All parameters specified with loaded outputs. 5. Duty cycle is measured at 1.5V. 6. A LOW and HIGH time of 12 ns corresponds to a PCICLK frequency of 33.33 MHz. For PCICLK frequencies of 30 MHz and 25 MHz, the LOW and HIGH times are each respectively 13.33 ns and 16 ns.
Switching Waveforms
Duty Cycle Timing
t1B
t1A 1.5V 1.5V
1.5V
2267-c
5
CY2267
Switching Waveforms (continued)
CPUCLK Outputs HIGH/LOW Time
t1C OUTPUT 2.4V 2.4V 0.4V 3.3V 0.4V 0V
2267-d
t1D
All Outputs Rise/Fall Time
2.0V 0.8V t2 t3 2.0V 0.8V t2 t4 3.3V 0V
2267-e
OUTPUT
Clock Skew
1.5V
CPUCLK-CPUCLK
1.5V
2267-f
t5
CPU-PCI Clock Skew
CPUCLK 1.5V
PCICLK t6
1.5V
2267-g
6
CY2267
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done. The Application Circuit is shown below.
Application Circuit
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F- 22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
7
CY2267
Test Circuit
VDD
1 0.1 F 4 VDD 0.1 F
32 0.1 F 29
8
26 0.1 F
11
23
14 0.1 F
20
OUTPUTS CLOAD
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code CY2267PVC-1 Document #: 38-00534-A Package Name O34 Package Type 34-Pin SSOP Operating Range Commercial
8
CY2267
Package Diagram
34-Pin Shrunk Small Outline Package O34
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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